1. Field of the Invention
This invention relates to a data processing system and more particularly to a microsequencer circuit used in a sequential type microprocessor for increasing the speed of microcode/control word access and generation.
2. Background Information
It is known that data processing systems generally comprise a central unit, a main memory and plurality of peripheral units connected to the central unit by means of a plurality of input/output channels for the exchange of information. The data processing system functions by processing data according to well defined program instructions. From a logical point of view, the central unit comprises a control unit and an operative unit. The program instructions are interpreted and executed by means of microprograms which are microinstruction sequences read from a control memory by the control unit, one microinstruction at a time. Through suitable decoding the microinstructions generate a set of elementary commands, or microcommands, which cause the operation of several logic networks of the central unit in the manner required by the several program instructions.
Generally, the control unit includes a program counter which enables the control unit to sequentially execute the program instructions. However, the execution of a program instruction may cause an interruption in the sequential execution thereof in order to execute a subroutine. All of the information regarding the status of the interrupted process must be saved in order to resume such process once the subroutine has been executed. One known technique for solving this problem includes a register file or RAM partition dedicated to a push-down stack function where each consecutive branched-from address is stored in a last in/first out order. This technique requires the skipping of machine cycles in order to access the register file or RAM partition.
Another known technique includes the use of a plurality of control store memories. A first control store memory contains the primary microinstruction group, a second control store memory contains a branched-to subroutine microinstruction group and possibly a third control store memory contains tertiary branched-to subroutine microinstruction groups. In such a configuration, a branched-from address must be stored prior to accessing the secondary or tertiary control store memories. Moreover, after the subroutine has been executed, machine cycles must be skipped in order to access the branched-from address in order to resume the execution of the primary microinstruction group.
Consequently, there is a need for a microsequencer which overcomes the necessity for skipping machine cycles in order to access the branched-from address.